The present invention is generally directed to tristate logic buffer circuits and is particularly directed to enhancing the dynamic response of such a circuit when providing a "high" logic level in the digital data output signal of the circuit.
A typical prior art tristate logic buffer circuit is shown in FIG. 1. This circuit includes an input transistor Q1, a phase splitter transistor Q2, a pull-down output transistor Q3, a pull-up transistor Q4, a current amplifying transistor Q5, first resistance R1, a second resistance R2, a third resistance R3, a fourth resistance R4, a fifth resistance R5, a diode D1 and an inverter 10. The circuit also has a data input terminal 12, a data output terminal 14, a circuit disable terminal 16, and a circuit control terminal 18.
The input transistor Q1 is a multi-emitter transistor, having a first emitter connected to the data input terminal 12 for receiving a digital data input signal. The first resistance R1 couples the base of the input transistor Q1 to the voltage supply terminal V.sub.cc. The phase splitter transistor Q2 has its base coupled to the collector of the input transistor Q1. The second resistance R2 couples the collector of the phase splitter transistor Q2 to the voltage supply terminal V.sub.cc. The pull-down output transistor Q3 has its base coupled to the emitter of the phase splitter transistor Q2, its emitter coupled to a circuit ground terminal, and its collector connected to the data output terminal 14. The third resistance R3 is connected between the base and emitter of the pull-down output transistor Q3. The pull-up output transistor Q4 has its emitter connected to the data output terminal 14, its collector coupled through the resistance R4 to the voltage supply terminal V.sub.cc and its base coupled through the current amplifying transistor Q5 to the collector of the phase splitter transistor Q2. The current amplifying transistor Q5 has its emitter connected to the base of the pull-up output transistor Q4, its base connected to the collector of the phase splitter transistor Q2, and its collector connected to the collector of the pull-up output transistor Q4. Resistance R5 is connected between the base of the pull-up output transistor Q4 and circuit ground.
The circuit disable terminal 16 is connected to a second emitter of the input transistor Q1, and is coupled to the circuit control 18 terminal through the inverter 10. The diode D1 has its anode connected to the collector of the phase splitter transistor Q2 and its cathode connected to the circuit disable terminal 16. The circuit is disabled when a "high" logic signal is applied to the circuit control terminal 18, whereby the inverter 10 causes a "low" logic signal to be applied at the circuit disable terminal 16.
When a "high" logic signal is applied at the circuit disable terminal 16, a digital data output signal that is the logical complement of the digital data input signal at input terminal 12, is provided at the data output terminal 14. When a "low" logic signal is applied at the circuit disable terminal 16, the circuit has a high output impedance between the data output terminal 14 and circuit to inhibit the provision of the digital data output signal at the output terminal 14.
It is an object of the present invention to enhance the dynamic response of the pull-up output transistor in providing a "high" logic level digital data output signal.